1. Field of the Invention
The invention relates to a semiconductor device and more particularly to a three-dimensional memory array with high density.
2. Description of Related Art
Advancements in electronic devices lead to the need for greater storage capabilities. In order to increase storage capability, the size of memory devices becomes smaller and more compact. Thus, the industry now pays high attention to three-dimensional (3D) memory arrays with high density.
FIG. 1 illustrates a schematic 3D diagram of a conventional 3D cross point memory array. A conventional 3D cross point memory array 10 includes a plurality of first electrodes 12 arranged along a first direction, a plurality of second electrode 16 arranged along a second direction, and a plurality of first memory elements 14. The second direction is perpendicular to the first direction. The second electrodes 16 are disposed above the first electrodes 12. The first memory elements 14 are disposed at cross points of the second electrodes 16 and the first electrodes 12. When a feature size of the fabrication is F, the smallest size of a memory cell in the 3D memory array is 4F2.
The 3D cross point memory array 10 can further include a plurality of third electrodes 20 arranged along the first direction above the second electrodes 16 and a plurality of second memory elements 18 disposed at cross points of the third electrodes 20 and the second electrodes 16. An equivalent smallest size of a memory cell in the 3D memory array is thus 2F2. Similarly, when the 3D memory array has N layers of memory cells stacked together, an equivalent smallest size of the memory cell is then 4F2/N.
Although capable of reducing the smallest size of the memory cell effectively, the conventional 3D cross point memory array fails to enhance the feasibility thereof due to the following reasons. Firstly, for every layer of memory cells stacked, at least one patterning step is required (including deposition, photolithography, etching and so on) which leads to high fabrication cost. In addition, since each layer of memory cells is formed in different patterning steps, the size and the composition thereof are not entirely identical and create variability to the characteristics of the device. Moreover, a lower memory layer (e.g. the first memory element 14) is subject to more thermal budget than an upper memory layer (e.g. the second memory element 18). Consequently, the lower memory layer has low reliability and performance.